This invention relates to programmable logic arrays and, in particular, to emitter coupled logic programmable logic arrays. Accordingly, it is a general object of this invention to provide new and improved arrays of such character.
In the past, programmable logic arrays were TTL in character. That is, they utilized transistor to transistor logic. Such prior art arrays were obtained by using AND OR circuits, wherein the outputs of AND gates fed OR circuits in the configuration. A further description of a prior art TTL programmable logic array is set forth hereinafter following the Brief Description of the Drawings.
Emitter coupled logic circuits which perform simple logic functions, in general, are known. Because the transistors are operated in the nonsaturating mode, emitter coupled logic is capable of extremely high speed operation. A universal logic gate utilizing emitter coupled logic was disclosed in U.S. Pat. No. 3,925,684 issued Dec. 9, 1975 to Gaskill, Jr. et al. Various Logic functions could be performed by varying the external connections to one or more universal logic gates. Programmable logic arrays were disclosed by Cavaliere et al in "Current Switch Read-Only Programmable Logic Array"; IBM Technical Disclosure Bulletin; Vol. 18, No. 10, pp. 3245-3248; March 1976. The arrays shown therein included two complete transistor arrays. Array logic for a read only memory was disclosed in U.S. Pat. No. 3,735,358 issued May 22, 1973 to Ho.
It is desirable to construct a multi-element programmable logic array in a monolithic integrated circuit utilizing emitter coupled logic in order to simultaneously obtain high packaging density and high operating speed. To achieve high packaging density, array elements of minimum area are required. The implementation of arrays using emitter coupled logic requires a circuit having a regular structure. Since the same circuit is repeated many times in an array, the circuit utilized requires not only minimum area, but also must lend itself to simple interconnection.